Volatile and non-volatile memory devices such as Dynamic Random Access Memory (DRAM), embedded-DRAM, Magneto-resistive Random Access Memory (MRAM), FLASH, etc. store bits of information in arrays of memory cells. Each memory cell includes a storage element having the capacity to save one or more bits of information. For example, a DRAM memory cell typically includes an access transistor coupled to a storage capacitor. One bit of information is written to the storage capacitor by activating the word line coupled to the gate of the access transistor. The storage capacitor is then either charged or discharged via the bit line of the cell to store the information bit. The information can be subsequently read by activating the word line and sensing the signal on the bit line.
An MRAM cell stores information in a similar manner, except a magnetic storage element is employed instead of a capacitor. The magnetic storage element typically includes two ferromagnetic plates, each of which can hold a magnetic field. The ferromagnetic plates are separated by a thin insulating layer. One of the plates is a permanent magnet having a particular fixed polarity. The field of the other plate changes to match that of an external field applied by the cell bit line. Read and write operations are controlled by the word line coupled to the gate of the access transistor.
A FLASH memory cell includes a floating-gate transistor for storing one or more bits of information. The floating-gate transistor has two gates instead of one. An upper control gate is formed above an insulated floating gate. The floating gate is interposed between the control gate and the transistor channel. The upper control gate is actuated by the cell word line which controls whether the cell is being written to or read from. One active node (i.e., the source or drain node) of the floating-gate transistor is coupled to the bit line and the other node is coupled to a source line. Because the floating gate is electrically isolated by an insulating layer, any electrons placed on it via the bit line are trapped in the floating gate. This in turn modifies the threshold voltage of the access transistor which determines the state of information stored by the cell.
Some types of memory cells have buried word and bit lines. Memory cell word and bit lines may be buried by forming trenches in a semiconductor substrate and filling the trenches with metal such as Tungsten. Storage elements can be formed on the substrate surface or in the metal layers disposed above the substrate. For example, some types of DRAM cells have a buried word line formed above a buried bit line. The recessed bit line has a contact region coupled to an active region (i.e., the source or drain) of the DRAM access transistor. The other active region of the access transistor is coupled to the overlying storage capacitor.
Buried bit lines and bit line contact regions are vertically separated from overlying buried word lines by a predetermined distance to ensure proper memory cell operation. Buried word and bit line structures may be vertically insulated from one another by forming trenches in a semiconductor substrate above the buried bit line structures. The trenches are then filled with a dielectric material. The oxide is recessed to a particular depth using a timed etch process to form a spacer in the bottom of each trench. Metal is then deposited on top of the spacer to form the word lines. The spacer insulates the underlying bit line and bit line contact regions from the overlying word lines.
However, oxide spacers of this type have a thickness of at least 30 nm or greater and a variation of +/−15 nm when formed in the bottom of a word line trench using a timed etch process. A thinner oxide spacer is difficult to attain because of the poor depth control associated with timed trench-oxide etch processes. Moreover, timed trench-oxide etch processes may yield a large wafer center to wafer edge variation. Thus, thinner trench oxide spacers having less variability are not feasible with conventional approaches. A thinner oxide spacer of about 15 nm with less variation (e.g., +/−5 nm) is desired for reasonable memory device functionality when advanced semiconductor technologies are employed.